1. Field of the Invention
The present invention generally relates to on-chip trench capacitor structures and, more particularly, to trench capacitor structures which optimize capacitors for diverse applications without added process complexity. The trench capacitor structures have particular application as decoupling capacitors and as node capacitors that enhance the soft-error immunity in, for example, static random access memory (SRAM) cells.
2. Background Description
One of the attributes of a decoupling capacitor is that it should exhibit a time response comparable to that of typical circuits, ranging from 250-300 picoseconds (ps). Present trench decoupling capacitors suffer, however from long resistor-capacitor (RC) delays (in the range of nanoseconds (ns)). Thus, there is a need for a decoupling capacitor structure which has a high capacitance per unit area yet has a time constant comparable to typical circuit switching time constants.
Dense static random access memory (SRAM) cells resulting from advances in lithography and other technology enhancements are reaching the point where the amount of stored charge is not sufficient to prevent high rates of fails from alpha particles and cosmic rays. Thus, there is also a need for capacitor structures that can be connected to the nodes of SRAM cells to enhance the cell immunity to ionizing radiation without increasing cell size.
In both applications, a trench capacitor is desirable in integrated circuits (ICs). However, current trench capacitor structure designs are not optimized for use as either decoupling capacitors or a storage capacitors for use in SRAM cells to attain immunity to soft errors.